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C8051F380/1/2/3/4/5/6/7/C
7. Voltage Reference Options
The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage refer-
ence, the on-chip reference voltage generator routed to the VREF pin, the unregulated power supply volt-
age (V DD ), or the regulated 1.8 V internal supply (see Figure 7.1). The REFSL bit in the Reference Control
register (REF0CN, SFR Definition 7.1) selects the reference source for the ADC. For an external source or
the on-chip reference, REFSL should be set to 0 to select the VREF pin. To use V DD as the reference
source, REFSL should be set to 1. To override this selection and use the internal regulator as the reference
source, the REGOVR bit can be set to 1.
The BIASE bit enables the internal voltage bias generator, which is used by many of the analog peripherals
on the device. This bias is automatically enabled when any peripheral which requires it is enabled, and it
does not need to be enabled manually. The bias generator may be enabled manually by writing a 1 to the
BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in
The C8051F380/1/2/3/C devices also include an on-chip voltage reference circuit which consists of a
1.2 V, temperature stable bandgap voltage reference generator and a selectable-gain output buffer ampli-
fier. The buffer is configured for 1x or 2x gain using the REFBGS bit in register REF0CN. On the 1x gain
setting the output voltage is nominally 1.2 V, and on the 2x gain setting the output voltage is nominally
2.4 V. The on-chip voltage reference can be driven on the VREF pin by setting the REFBE bit in register
REF0CN to a 1. The maximum load seen by the VREF pin must be less than 200 μA to GND. Bypass
capacitors of 0.1 μF and 4.7 μF are recommended from the VREF pin to GND, and a minimum of 0.1uF is
required. If the on-chip reference is not used, the REFBE bit should be cleared to 0. Electrical specifica-
Important Note about the VREF Pin: When using either an external voltage reference or the on-chip ref-
erence circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar.
Refer to Section “20. Port Input/Output” on page 153 for the location of the VREF pin, as well as details of
how to configure the pin in analog mode and to be skipped by the crossbar.
REF0CN
To ADC, IDAC,
IOSCEN
EN
Bias Generator
Internal Oscillators,
Reference,
TempSensor
VDD
External
EN
Temp Sensor
To Analog Mux
Voltage
Reference
R1
Circuit
VREF
1x/2x
1.2V Reference
EN
REFBE
GND
0
REFBGS
0
4.7 ? F
+
0.1 ? F
VDD
1
VREF
(to ADC)
Recommended Bypass
Capacitors
Internal
Regulator
1
REGOVR
Figure 7.1. Voltage Reference Functional Block Diagram
62
Rev. 1.4
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